1. Technical Field
This invention relates generally to assigning interrupts for input/output (I/O) devices among nodes of a system, and more particularly to assigning such interrupts among the processing nodes of a non-uniform memory access (NUMA) computer system.
2. Background Art
Input/output (I/O) device interrupt assignment refers generally to identifying the target set of processors that will bear the responsibility for servicing interrupt(s) from a specific I/O device. The interrupt assignment for a device is usually determined during initialization of the device driver for the device. A device's processor interrupt assignment can be as narrow as one processor, or as broad as all the processors within a system. Some operating systems use a round-robin approach to distribute the interrupt handling burden across the nodes of a system, assigning a given interrupt to all the of the processors within a given node selected to handle that interrupt.
However, such approaches do not necessarily optimally distribute the I/O device interrupt burden across nodes and processors for cache-coherent (cc) non-uniform memory access (NUMA) systems. In a NUMA system, access time to and from processors and memory is non-uniform, varying by processor and memory region. Specifically, access time from processors to I/O devices and between I/O devices and memory may vary. Round-robin approaches for assigning interrupts do not leverage such topologies of NUMA systems. For instance, the interrupt service routine (ISR) for an I/O device may reside on a first NUMA node, whereas the I/O device may itself be connected to a second NUMA node. A round-robin approach may very well select yet a third node to handle the interrupts for the device, causing the interrupt to be routed roundabout from the second node (at the device) to the round-robin-assigned third node, and from there to the second node where the ISR resides.
Such an example represents the degenerate case in which all interrupt processing is cross-nodal. That is, the node at which the memory storing the ISR resides is remote with respect to the interrupt-servicing processor's node, and both of these nodes are remote to the node at which the I/O device is connected. Furthermore, round-robin approaches do not distinguish between types of I/O devices when assigning device interrupts. Therefore, performance-critical I/O devices are treated the same as other I/O devices. Consequently, all the interrupts for performance-critical devices may be assigned to the same node, which can result in decreased system performance.
For this reason, as well as other reasons, there is a need for the present invention.